Design of Avalanche Capability of Power MOSFETs by Device Simulation

The avalanche behavior of new 150 V trench power MOSFETs was designed with the help of two- dimensional device simulation techniques. The devices employ the compensation principle for low on-state losses. A new edge-termination structure ensures that avalanche breakdown always occurs in the cell region of the device. For the transistor cells, two different destruction regimes were identified: energy-related destruction and current-related destruction. Possible simulation approaches to account for the different effects were proposed. The found dependence on design parameters based on device simulation was qualitatively confirmed by experimental results. Furthermore, strong dependence between on-resistance and avalanche current was shown.