Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

In this paper, we present the design theory and fabrication process integration of 65 nm and 32 nm node Si and Si
_1-x
Ge
_x
vertical dual carrier field effect transistor (VDCFET) CPU for arrays of parallel computers. The design theory includes the design of complementary VDCFET devices and their high speed circuits. The fabrication process includes molecular beam epitaxy, electron beam lithography, selective ion implantation and shallow trench isolation of "silicon on insulator" substrate. The effective channel lengths of 65 nm node and 32 nm node Si VDCFET have been reduced to 18 nm and 9 nm respectively.