Design of a low-power digital core for passive UHF RFID sensor

A digital section of a passive UHF RFID sensor based on Auto-ID Center's Class 0 Protocol. Several low-power techniques both at system and circuit level are adopted to reduce the total power consumption. The power consumption of the Digital Core is 8.9 muW under the 2V power supply excluded the Memory. Physical implementation on Chartered 0.35 um 1P4M process has been carried out and the chip is being fabricated. Functional verification have been successfully performed by means of an FPGA develop board.