A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

This paper presents a 6-digit Analog-to-Quatemary Converter (AQC) using a 0.35μm CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDF, SFDR and THD of 65.17dB, 73.89dB and -73.26dB at 2.5V supply voltage and 50MHz sampling rate.