Design theory and fabrication process integration of 32nm node Si, Ge and Si1-xGex vertical dual carrier field effect transistor SOC for switching and communication applications

With the annoucement of Intel and IBM to provide 45nm CPUs, the semiconductor industry has been engaged in the research and development work of 32nm node CMOS technology. In this paper, we present our development work on the design theory and fabrication process integration of 32nm node Ge, Si and Si
1-x
Ge
x
“Vertical Dual Carrier Field Effect Transistor” (VDCFET) ASIC for switching and small signal communication applications. The effective channel length of our 32nm node Ge, Si and Si
1-x
Ge
x
switching VDCFET have been reduced to 9nm. The effective channel length of our 32nm node Ge, Si and Si
1-x
Ge
x
communication small signal VDCFET has been reduced to 5nm. The merits of these Ge, Si and Si
1-x
Ge
x
32nm node VDCFET shall be compared.