Metal Electrode/High-$k$ Dielectric Gate-Stack Technology for Power Management

High-
k
dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO
₂
-based gate dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying high-
k
dielectric has been expanded, and various CMOS device results with metal electrode/high-
k
gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high-
k
gate dielectric stacks to future technology generations. A new class of high-
k
dielectric that has a dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher
k
dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.