Mapping Applications on Coarse-Grained Reconfigurable Systems Using Architecture Template Modeling

We introduce a novel architecture template modeling for mapping applications on coarse-grained reconfigurable SoC. System level design issues become critical with increasingly complex integrated circuits and time-to-market pressure continues relentlessly. Design reuse and early design decision for computation and communication are a "must". Our technique is based on a transaction level architecture template modeling methodology in which computation/communication co-design is performed with the architecture described in an abstract manner. Besides, we use eACOGA algorithm for hw/sw partition. eACOGA uses genetic algorithm to evolve the parameters of ant colony optimization, and makes use of such advantages as positive feedback and efficient convergence to search for optimal partition solutions. Experiments show our approach improves the quality and efficiency of hw/sw partition for reconfigurable SoC, and architecture template enhances system reuse of existing SoC design and achieves exploration speedup well.