3D Capacitive Interconnections for High Speed Interchip Communication

A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13
μ
m CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15×15
μm²
a wide range of operating frequency up to 900
MHz
with an energy consumption of
41fJ/bit
. In the asynchronous scheme we demonstrate with electrodes 8×8
μm²
a vertical propagation of clock at
1.7GHz and a propagation delay of 420ps for general purpose signal with energy consumption of 80fJ/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 10¹³ bits transmitted.