A linearity and power efficient design strategy for architecture optimization of gm-C biquadratic filters

To limit design time for the large range of specifications resulting from the multitude of modern communications standards, a good design strategy for analog circuits is essential, even within a given building block. This paper presents an efficient approach to design biquadratic sections for a low-pass baseband filter based on the g
_m
-C architecture. Starting from high-level specifications, the proposed methodology completely determines the biquad's architecture level for linearity and power optimization. As an illustration, a 10 MHz bandwidth Butterworth biquad section optimized for power and linearity applying the proposed design flow has been successfully designed in a 0.13 mum CMOS technology with a 1.2V supply voltage. It achieves a SFDR of 67 dB for a power consumption of only 3 mW.