CDM tests on interface test chips for the verification of ESD protection concepts

The CDM failure threshold of microelectronic components are determined by the peak value of the discharge current. The requirements of the market, however, are given in terms of potential. In addition, it is not known how the CDM susceptibility of an IC is affected by its core circuitry. This paper introduces an idea how CDM protection concepts can be checked by tests on an interface test chip to guarantee satisfying product qualifications.