A pageable, defect-tolerant nanoscale memory system

As we scale down to the nanoscale regime, manufacturing defects will increase significantly. With expected bit error rates as high as 2–10%, the reliability of a contiguous 4 K-Byte memory page falls off to zero. We propose a powerful combination of static and dynamic techniques to tackle this problem. Using a combination of defect mapping, error correction, and sparing, we can achieve approximately 46.5%, 26.1% and 13.2% storage efficiency in contiguous 4 K-byte pages, given bit error rates of 2%, 5% and 10%, respectively. This result allows us to use standard virtual memory to map a contiguous virtual address space onto a nanoscale memory system with some bad physical pages, giving us a more usable system than previous approaches.