Structural and Electrical Properties of Ferroelectric-Gate Field-Effect-Transistors Using Au/(Bi,La)4Ti3O12/SrTa2O6/Si Structures

We fabricated the ferroelectric-gate field effect transistors (Fe-FETs) using a metal-ferroelectric-insulator-semiconductor (MFIS) structure as a gate configuration using (Bi,La)
₄
Ti
₃
O
₁₂
(BLT) and SrTa
₂
O
₆
(STA) thin films. From the capacitance-voltage (C-V) measurements for MFIS capacitors, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.5 V for the plusmn5 V bias sweep. The leakage current density was as low as 1x10
^-7
A/cm
²
at 5 V. From drain current-gate voltage characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) of the device was about 0.5 V due to the ferroelectric nature of BLT film. The drain current-drain voltage characteristics of the fabricated FeFETs showed typical n-channel FETs characteristics.