A study of dynamic reconfigurable FFT processor for OFDM based cognitive radio

Cognitive radio recognizes frequency use in space and time domains and improves frequency utilization efficiency and communication performance by selecting an optimal communication mode. This paper proposes a new method reducing circuit area for reconfigurable FFT processors with multiple communication modes in OFDM based cognitive radio. The proposed method offers the FFT stages with two dimensional arrays and dynamically changes the data path connections in the butterfly and FIFO memory blocks. In the CMOS implementation, this structure has reduced circuit area by 35% compared with the conventional circuit.