An improved model for representing current waveforms in CMOS circuits

A resistance-inductance-capacitance (RLC) model is described for estimating current waveforms in digital CMOS circuits. The model is based on parameters that are readily derived from information available in board layout files and component data sheets or IBIS (I/O buffer information specification) files. Compared with the simpler triangular waveform traditionally used to approximate current in CMOS circuits, the RLC model more accurately estimates the shape of the current waveform in the time domain and the amplitudes of the upper harmonics in the frequency domain.