Compact Macromodeling of High-Speed Circuits via Delayed Rational Functions

This letter introduces a new method for compact macromodeling of high-speed circuits with long delays, characterized by tabulated time-domain data. The algorithm is based on partitioning the response and subsequently approximating each partition with a low-order sum-of-exponentials, delayed in time-domain. This results in a compact low-order macromodel in the form of delayed-differential equations, which can be efficiently analyzed using SPICE like simulators.