Analysis of a Passive Sensor for Predicting Process-Induced Stress in Advanced Integrated Circuit Interconnect

Process-induced stress and its deleterious effects on interconnect reliability become increasingly severe as current densities escalate at scaled geometries. Accurate and reliable measurements of stress are paramount to understand the failure mechanisms in advanced interconnect schemes, the control of process technologies, the integration of new materials, and the reliability-driven architecture design. An analytical model of a recently developed passive strain sensor that is suitable for predicting process-induced stress in advanced interconnect technology is presented. This passive strain sensor is scalable for future interconnect geometries predicted by the International Technology Roadmap for Semiconductors. The model is developed using complementary energy principles and is compared against the available experimental data on aluminum interconnect. Agreement between the model and the experiment is shown to be within 5%. The use of the developed model enables critical design parameters to be identified and optimized for any level of stress. Furthermore, as the model is scalable, it will facilitate the design of such sensors for future interconnect geometries.