A Novel Latch-Up Protection for Bulk-Silicon Scan Driver ICs of Shadow-Mask Plasma-Display Panel

This letter reports a low-cost and excellent latch-up protection technology for bulk-silicon scan driver ICs of shadow-mask plasma-display panel (SM-PDP) by integrating a 100-V lateral double-diffused (LD) MOS and a standard low-voltage (LV)-CMOS control circuit. The technology is implemented using an N+ guard ring in the LV-n-well, a P+ guard ring in the p-substrate near the LV-nMOS, and a deep high-voltage (HV)-n-well and a p-drift guard ring between the HV-nLDMOS and LV-CMOS circuits. The experiment results show that the latch-up in the LV-CMOS circuits is avoided when the scan ICs are applied with -340 V during the sustain periods.