Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As/In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ p-HEMTs

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In
_0.52
AI
_0.48
As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In
_0.52
Al
_0.48
As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G
_m,max
(1.38 S/mm), I
_ON
n/I
_OFF
(1.18X10
⁴
), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V
_th,avg
= -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.