FPGA Implementation of a Low Complexity Efficient Traceback Viterbi Decoder for Wireless Applications

Convolutional coding is a coding scheme often employed in deep space communications and more recently in digital wireless communications. Viterbi decoders are used to decode convolutional codes. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this project, a novel architecture, low-complexity design of Viterbi decoders for wireless applications is proposed. The focus of my design is the modified trace back approach for final decoding. A 4 state Viterbi decoder following the proposed architecture is implemented and the synthesis results are presented. Testing is done by simulating the synthesized model on MODEL SIM.