Avalanche electron injection in 4-nm Si/sub 3/N/sub 4//8-nm SiO/sub 2/ dielectric structure: turn-around phenomenon and Si-SiO/sub 2/ interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si/sub 3/N/sub 4/+8-nm SiO/sub 2/) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si/sub 3/N/sub 4/ interface) and subsequent trapping near the SiO/sub 2/-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO/sub 2/-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping.<
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