Acceleration of finite field arithmetic algorithms in embedded processing platforms utilizing instruction set extensions

Finite field arithmetic is essential to error correction and cryptography. Instruction set extensions are an alternative to ASICs and DSPs while providing the same performance with embedded CPUs. An instruction set extension is presented that handles various fields in GF(2
^m
). A MIPS DLX processor core is accelerated using an auxiliary processing interface to a finite field arithmetic unit. Additional instructions are added to the DLX core set which are used to create finite field arithmetic benchmarks. The processor core and extensions datapath are synthesized in a standard cell 0.18μm CMOS process achieving a 233MHz clock. The combined DLX and FFU system demonstrates a 355× speed-up when performing elliptical curve projective point doubling in GF(2
¹⁶³
).