Yield implications and scaling laws for submicrometer devices

Yield scaling laws are developed that are applicable to VLSI (very large-scale integration) devices with features of minimum dimension smaller than that at which the defect-size probability density function peaks. Expressions for the fault-probability kernel of reduced-size devices are derived in terms of the full-size or prototype device. The role of the defect-size probability density function with respect to the average fault probability is explained and expressions for it are developed. The ensuing scaling laws are utilized to obtain expressions for the expected number of faults, and then applied to the evaluation of the yield for several different cases. The implications of the results for yield and productivity are examined.<>