Low-Transition Test Pattern Generation for BIST-Based Applications

A low transition test pattern generator, called LT-LFSR, is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions; 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures. The proposed architecture reduces the correlation among the patterns generated by LT-LFSR with negligible impact on test length. The experimental results for ISCAS'85 and '89 benchmarks confirm up to 77% and 49% reduction in average and peak power, respectively.