Millimeter wave design with 65 nm LP SOI HR CMOS technology

In this paper, we present active and passive performances of the 65nm LP SOI HR technology from STMicroelectronics and two simulated circuits to illustrate the potentiality of the technology for millimeter wave (mm-wave) applications. 65nm Low Power (LP) Partially Depleted (PD) n-MOSFET Floating Body (FB) shows a f√f
_max
of 160/200GHz. Coplanar Waveguides (CPW) present a measured attenuation constant lower than 1dB/mm at 60GHz for 45Ω and 70Ω characteristic impedance (Zc). The 60 GHz simulated Low Noise Amplifier (LNA) shows 22dB gain, an input/output reflection losses <-14dB and a noise figure (NF) of 5.5dB while dissipating 72mW under a 2.4V supply. The resistive drain pumped mixer shows 7.7dB conversion losses, a NF of 12dB for a P
_LO
=-5dBm (local oscillator power). This architecture shows a simulated linearity performance IP
_1dB
of - 10dBm and an IIP
₃
of 0dBm with μW power consumption.