Development of High-resolution Digital Vision Chip Based on CFPE Architecture

In this paper, we describe VLSI implementation using a new vision chip architecture that enables various visual processings on the same architecture and combines high speed and the high accumulation. A 64 × 64 pixel prototype vision chip and its evaluation results are shown. The chip is integrated on a 3.6 mm × 3.9 mm chip using a 0.35 μm CMOS DLP/TLM process; the pixel size is 33.0 μm × 33.0 μm. The maximum current consumption is approximately 500 mA.