A High-Security and Low-Power AES S-Box Full-Custom Design for Wireless Sensor Network

The advanced encryption standard (AES) S-box was the only non-linear structure of the AES algorithm; it dominated the hardware complexity of the AES cryptographic module. For Wireless Sensor Network applications, S-box must offer low power, small area and high security. In this paper, a full-custom S-box implementation with low-power, compact and well DPA- resistant property was proposed. The energy-efficient pass transmission gate (PTG) and three-input exclusive-OR (XOR) gate based on three-transistor XOR element were used to realize the functionality of S-box, it resulted in the reduction of the area tradeoff and power consumption. The PTG-based latches, controlled by asynchronous latch controllers, were inserted in the data path to block the propagation of the dynamic hazards. A countermeasure against differential power analysis, based on random delay insertion, was presented to attain high-security. The resulting implementation on a 0.25 mum CMOS process is very suitable for the source-limited wireless sensor node chips.