A Simple FASTBUS Multiple Segment Implementation

A simple FASTBUS multiple segment architecture has been implemented. Data transfer rates from the front end segments of up to 5 Mwords/sec have been measured. The implementation requires a LeCroy 1821 SM/I module and its accessory 1821/ECL interface card in each front end segment and a LeCroy 1892 FASTBUS memory in the MASTER segment. Data transfer does not require intervention by the HOST. Front end segment control is provided by the SM/I port of the 1892. Each 1892 can control up to 16 front end segments.