Status of the Interlaboratory Development of a High-Speed Standard Data Bus - FASTBUS

The FASTBUS project is an interlaboratory effort to develop a next generation laboratory standard data bus. The principal design goals are high speed (<100 nsec per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high energy physics applications. The current status of development is briefly described.