Prevention of CMOS Latch-Up by Gold Doping

A major disadvantage of bulk CMOS integrated circuits is that they can exhibit SCR behavior when exposed either to modest levels of ionizing radiation (· γ ≃ 108 rads (Si)/sec) or to an overvoltage (which is typically less than the substrate to p-well avalanche voltage). This paper discusses the successful application of gold-doping to CMOS integrated circuits to control substrate minority carrier lifetime, thus preventing latch-up. Data is presented showing the effects of the gold-doping upon junction integrity, oxide charge, surface state density, and radiation hardness. Junction arrays and split lots of a CMOS LSI circuit were fabricated to demonstrate that the gold-doped process does not reduce device yield. Data after bias-temperature stress-aging indicates that there is no statistically significant difference in the reliability between gold-doped and undoped CMOS circuits.