A P-Channel MOS IC for Educational Purposes Using a Two-Photomask Process

The two-photomask process for the fabrication of p-channel MOS devices provides a full introduction to the fundamental planar process. A 1000 A double layer insulator fim of silicon dioxide (700 Å) and silicon nitride (300 Å) is used for the gate and field regions of the devices. Using chemical vapor deposited boron nitride as the boron diffusion source eliminates the usual photo-process steps for the etching of the contact holes for the source and drain. The mask alignment tolerance can be designed to be within one half of the lateral diffusion length of 8 Mm. This process can be applied to a variety of devices and can be completed by engineering students in only three seven-hour laboratory days. Single chip inverters and RS flip-flop circuits are illustrated, along with an analysis of their parasitics.