High-Resolution and Multi-Channel Time Interval Counter Using Time-to-Digital Converter and FPGA

A high-resolution and Multi-Channel time interval counter is designed using Time-to-Digital Converter(TDC) and(Field-Programmable-Gate-Array) FPGA. The core of counter is the TDC chip which is interfaced to and controlled by FPGA . The Counter has 1 start channel and 8 stop channels and can be provided with four different modes, and thus four different resolutions. In the highest resolution mode, the counter demonstrates a statistical standard deviation of 18.6 ps. In the lowest resolution mode, that is 82ps, the counter can work with 8 channels and be endless measurement range by internal retrigger of start. The measurement data can be read from the two FIFOs which are part of TDC as a form of real-time transfer or block. Therefore, the counter is communicated with personal computer by serial port RS232. This configuration provides an simply and efficient way of using a computer not only to control and operate the counter, but also to store and process measured data.