Design of a Fuzzy Logic Coprocessor using Handel-C

Design and implementation of a fuzzy logic (FL) coprocessor is presented in this paper. The main goal of a FL coprocessor is to speed up the operations typical for FL algorithms. Current implementations of FL algorithms are dedicated and general purpose. The main drawback of solutions based on dedicated hardware is lack of configurability. Software implementation on general purpose processors is slow for many applications. The basic components of the FL coprocessor presented in this paper are designed in Handel-C using Celoxica's DK Design Suite. The inference engine inside the FL coprocessor is a Mamdani-type engine and the FL coprocessor only supports trapezoid and triangular membership functions. With the DK Design Suite, area estimations are analyzed and throughput is increased by applying pipelining and parallelism transformations.