Logic Suitability of 50-nm $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Beyond-CMOS Applications

We have experimentally studied the suitability of nanometer-scale $ \hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm-gate-length $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height $(\Phi_{B})$ and insulator thickness $(t_{\rm ins})$ on the logic characteristics of $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ HEMTs. The best 50-nm HEMTs with the highest $\Phi_{B}$ and the smallest $t_{\rm ins}$ exhibit an $I_{ \rm ON}/I_{\rm OFF}$ ratio in excess of $\hbox{10}^{4}$ and a subthreshold slope $(S)$ below 86 mV/dec. These nonoptimized 50-nm $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ HEMTs also show a logic gate delay $(CV/I)$ of around 1 ps at a supply voltage of 0.5 V, while maintaining an $I_{\rm ON}/I_{\rm OFF}$ ratio above $\hbox{10}^{4}$, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.