Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative-bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage ($V_{t}$) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent $V_{t}$ degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based $V_{t}$ model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: 1) static noise margin; 2) statistical read and write stability; 3) parametric yield; and 4) standby leakage current $(I_{\rm DDQ})$. We show that due to NBTI, read stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.