Record-low on-Resistance for 0.35 μm based integrated XtreMOSTM Transistors

Experimental data are shown for integrated smart power transistors breaking the silicon limit at 100 V. The performance is close to the much lower super-junction limit for the given device pitch. The device uses standard trench technology, and is implemented in a 0.35 μm smart power process. Key steps to improve the device performance yielding a record performance of 30 mOhm*mm
²
for a V
_bd
of 94 V, are highlighted in the paper.