Timing Jitter Modeling and Minimization for a Servo Track Writer

During servo track writing (STW), the timing jitter in clocking process can induce significant errors on servo pattern, which is known as phase-in error. In this paper, we measured the timing jitter on our STW setup and modeled the jitter sources in frequency domain. With the timing jitter models, the typical phase-locked loop system is taken as a typical closed-loop control system and loop shaping and control method are used to design the loop filter with objective to minimize the timing jitter. It is shown that timing jitter can be significantly reduced with loop filter designed with the H
₂
method.