An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10 Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a linked-list of the packet memory addresses which is maintained by the packet buffer controller. The architecture is pipelined and optimised to combat the latencies involved with RLDRAM II technologies to enable a high performance low cost packet buffer implementation.