A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm

In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also implemented. The DBF hardware implementation works at 72 MHz in a Xilinx Virtex II FPGA and it can code 30 CIF frames (352times288) per second. The power consumption of DBF hardware is analyzed and up to 13% power savings is achieved by applying clock gating and glitch reduction techniques to DBF datapath.