Total Leakage Power Optimization with Improved Mixed Gates

Gate oxide tunneling current I
_gate
and sub-threshold current I
_sub
dominate the leakage of designs. The latter depends on threshold voltage V
_th
while I
_gate
vary with the thickness of gate oxide layer T
_ox
. In this paper, we propose a new method that combines approaches of dual threshold CMOS (DTCMOS), mixed-T
_ox
CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant