FPGA Based Accelerator for Simulated Annealing with Greedy Perturbations

This paper discusses design of an field programmable gate array (FPGA) based hardware accelerator for a standard cell placement tool. A software program was used to determine the bottlenecks in the Simulated Annealing (SA) algorithm with greedy perturbations and dynamic cooling schedule. A solution implementing computing platform with specialized hardware configurations inside an FPGA was investigated as having the possibility to improve the efficiency of the SA-based algorithms.