Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

We describe a low-temperature polymer-based 3D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340
^o
C. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3D inverter circuit along with demonstration of four-device-layer 3D integrated stack are presented.