Low Power Design from Technology Challenge to Great Products

Each generation of semiconductor process technology enables increased levels of integration and density on a single chip, Moores Law continues to prevail and the users of portable and hand held communications and entertainment products enjoy greater functionality and features. Lifestyles and user paradigms indicate that no matter how many features are added, service providers and manufacturers think of more and users cannot wait to acquire the latest products. Features, performance, fashion and, of course, fierce competition, drive the market and thereby set the challenge for the semiconductor designer. The challenge for designers is to create systems on a single chip (SoC) to provide these features for the user and to enable service and content providers to realize new emerging market opportunities. This has been a challenge for many years but, now that nanometer process technologies form the enabling process technology, the design challenge is much greater. Nanometer design effects must be considered from the initial SoC architecture all the way through to manufacturing where design for manufacturing (DFM) effects must be overcome to enable reliable, high volume production. At the silicon level the features demanded by the users require extensive efforts to provide acceptable performance and reliability. Users of cell phones, PDAs and MP3 players will be most familiar with the need for long battery life while, to achieve this, the SoC designer worries about how to design with lower supply voltages, higher leakage currents, on chip power density and reliability. Packaging techniques which assemble multiple chips to form systems in package (SiP) also create signal integrity and power dissipation issues. At the same time designers must be able to design with EDA design tools and methodology's that are still emerging and where no standards for low power design exist today to make the task easier. This keynote will talk about the low power design techniques available to SoC designers, how they are implemented in SoCs and how they are implemented in existing and new designs. The talk will end with a view on the challenges coming up next and what needs to be done to prepare for them