Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs

We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presenited approach builds on an iterative optimization step during the model generation phase.