A High-Performance Low Cost SAD Architecture for Video Coding

This paper presents a high-performance low cost sum of absolute difference (SAD) architecture for motion estimation, which consumes a lot of computation and resource in video coding. Unlike many hardware implementations based on complement adders, this paper features the comparison of unsigned numbers to generate partial results of SAD and determine minimum SAD. Furthermore, the compression array unit is implemented by 4-2 compressor. This general-purpose architecture is implemented with a 2-stage pipeline and it is suitable for block-based video compression standards, such as MPEG-4, H.263 and H.264/AVC. Performance analysis shows that compared with other SAD architectures, the proposed architecture reduces 15.3%-22.9% area at almost no cost of latency.