Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools

The evolution of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning future ULSI technology is whether MOSFET devices can be scaled to 100nm channel length and beyond for continuing density and performance improvement. In this paper, the design, fabrication and characterization of high-performance and low-power 90nm channel length MOSFET devices are described. Several parameters have to be scaled down such as gate oxide thickness, channel length, ion implantation for threshold voltage adjustment and other specifications to achieve desirable electrical characteristic. To control the short-channel effect (SCE) and hot-carrier reliability that limits device scaling, lightly doped drain (LDD) structure, shallow junction of drain / source and Shallow Trench Isolation (STI) are implemented. Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools is used for fabrication and simulation of CMOS transistor namely ATHENA and ATLAS. Simulations using these programs provided the opportunity to study the effect of different device parameters on the overall device performance. The devices were simulated and gradually the performance of each one was improved, until an optimal device configuration was created for a particular application.