Design and Simulation of a High Performance Lateral BJTs on TFSOI

Lateral BJT's have received renewed interest with the advent of BiCMOS and Silicon on Insulator (SOI) technology. It's been reported in [1] that a 67 GHz f
_max
novel lateral BJT's on TFSOI has been fabricated with a simplified process. This paper presents an investigation of this high performance transistor by using 2D process and device numerical simulation. Accurate geometrical structure and reasonably good doping profiles with a simple fabrication process are successfully achieved in the process simulation. However, a careful attention is required to define the mesh for the device to obtain an accurate measurement of device characteristics. With a base, low-doped collector, emitter and high-doped collector concentrations of 3 × 10
¹⁷
cm
^-3
, 1.0 × 10
¹⁷
cm
^-3
, 5 × 10
²⁰
cm
^-3
and 3 × 10
²⁰
cm
^-3
respectively, a variation of 0.1-0.13μm base width is observed. I-V and frequency performance of these transistors are simulated and analyzed. Y-parameter measurement at frequency 10 MHz - 1000 GHz shows a 21 GHz f
_max
was successfully achieved at V
_BE
=0.7V, V
_CE
=2.0V and I
_CE
=6.0μA.