Notice of Violation of IEEE Publication Principles: A 10GHz Low Phase Noise 0.13μm CMOS LC-VCO for Mixed Signal SoCs Using Noise Rejection Caged Inductors

Notice of Violation of IEEE Publication Principles

"A 10GHz Low Phase Noise 0.13μm CMOS LC-VCO for Mixed Signal SoCs Using Noise Rejection Caged Inductors"
by A. Maxim,
in the Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE
3-5 June 2007 Page(s):693-696

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici D. Smith S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
Several coupled noise rejection techniques are proposed for LC oscillators operating in noisy mixed signal SoC environment. A simple metal guard ring around the LC-VCO can achieve up to lOdB of coupled noise rejection with a minimal area penalty and no additional processing steps. The best noise rejection (>60dB) was achieved with a full metal cage realized both in IC metal layers and in thick package layers. A compromise between cost, area and performance was achieved with a partial metal cage with no top plate and having graded lateral walls and a grid type bottom plate halo. Spur rejection up to 35 dB with only a 10% penalty in inductor quality factor were achieved. The different inductor structures were realized in 0.13 mum CMOS and the phase noise and spur rejection capability were investigated while operating on the same die with a large digital core.