Materials and processes for high signal propagation performance and reliable 32 nm node BEOL

Integrated circuits are more and more impacted by interconnect performance. As size reaches nanometric dimensions, changes in materials aim at performing a reliable and compliant technology with a maximum capability to reduce delay time and power consumption. At the 32 nm node, k value reduction of existing porous SiOCH and optimization of metallization with thin barrier, conformal seed and plating should mitigate RC and offer an improvement compared to current materials of the 45 nm node.