Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification

The formal verification of optimized arithmetic circuits imposes several challenges. Performance-optimized IEEE floating-point implementations can be particularly hard verification cases for their size and their irregularities, for the redundancy that is often used in the representations of intermediate values, and by the complex non-standard logic optimizations that are incorporated in the designs. We formally verify the highly optimized Even-Seidel rounding algorithm for IEEE floating-point multiplication and IEEE floating-point addition which incorporates the use of rounding injections. Our verification efforts are based on the PVS theorem-prover. We structure the whole verification process in a hierarchical fashion where existing specifications and properties are re-used to ease the overall effort. We show the benefits of our hierarchical approach by verifying two variants of the algorithm for performance optimized IEEE floating-point multiplication and IEEE floating-point addition.