An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology

A low power successive approximation analog-to-digital converter is presented operating at 1.2 V supply. The circuit has been designed in a 0.13 μm standard CMOS technology. The power consumption while converting is 13 μW, and in standby mode the power is reduced to 5.8 μW. The resolution is programmable between 1 to 8 bits. It can work from 500 Hz up to 50 kHz clock frequencies.